/*
 * _001_Blink_PC5_ATmega8.asm
 *
 *  Created: 24.06.2014 7:19:04
 *   Author: ?????
 */ 

 	;.include "m8def.inc";
	;.include "macro.inc";
 
; RAM ===================================================
	.DSEG
; END RAM ===============================================

; FLASH ======================================================
	.CSEG
		.ORG $000     RJMP Reset ; (RESET) 
		.ORG INT0addr RETI       ; (INT0) External Interrupt Request 0
		.ORG INT1addr RETI       ; (INT1) External Interrupt Request 1
		.ORG OC2addr  RETI       ; (TIMER2 COMP) Timer/Counter2 Compare Match
		.ORG OVF2addr RETI       ; (TIMER2 OVF) Timer/Counter2 Overflow
		.ORG ICP1addr RETI       ; (TIMER1 CAPT) Timer/Counter1 Capture Event
		.ORG OC1Aaddr RETI       ; (TIMER1 COMPA) Timer/Counter1 Compare Match A
		.ORG OC1Baddr RETI       ; (TIMER1 COMPB) Timer/Counter1 Compare Match B
		.ORG OVF1addr RETI       ; (TIMER1 OVF) Timer/Counter1 Overflow
		.ORG OVF0addr RETI       ; (TIMER0 OVF) Timer/Counter0 Overflow
		.ORG SPIaddr  RETI       ; (SPI,STC) Serial Transfer Complete
		.ORG URXCaddr RETI       ; (USART,RXC) USART, Rx Complete
		.ORG UDREaddr RETI       ; (USART,UDRE) USART Data Register Empty
		.ORG UTXCaddr RETI       ; (USART,TXC) USART, Tx Complete
		.ORG ADCCaddr RETI       ; (ADC) ADC Conversion Complete
		.ORG ERDYaddr RETI       ; (EE_RDY) EEPROM Ready
		.ORG ACIaddr  RETI       ; (ANA_COMP) Analog Comparator
		.ORG TWIaddr  RETI       ; (TWI) 2-wire Serial Interface
		.ORG SPMRaddr RETI       ; (SPM_RDY) Store Program Memory Ready
	.ORG   INT_VECTORS_SIZE
	
; Interrupts ==============================================
; End Interrupts ==========================================

; INITIALIZATION ==========================================
	;;; Initialize stack
	Reset:		LDI R16,Low(RAMEND)
				OUT SPL,R16
				LDI R16,High(RAMEND)
				OUT SPH,R16
 
; Start coreinit.inc
	;;; Initialize RAM
	RAM_Flush:	LDI ZL,Low(SRAM_START)
				LDI	ZH,High(SRAM_START)
				CLR	R16
	Flush:		ST 	Z+,R16
				CPI	ZH,High(RAMEND)
				BRNE Flush
				CPI ZL,Low(RAMEND)
				BRNE Flush

	;;; Initialize REGs
				CLR	ZL
				CLR	ZH
				CLR	R0
				CLR	R1
				CLR	R2
				CLR	R3
				CLR	R4
				CLR	R5
				CLR	R6
				CLR	R7
				CLR	R8
				CLR	R9
				CLR	R10
				CLR	R11
				CLR	R12
				CLR	R13
				CLR	R14
				CLR	R15
				CLR	R16
				CLR	R17
				CLR	R18
				CLR	R19
				CLR	R20
				CLR	R21
				CLR	R22
				CLR	R23
				CLR	R24
				CLR	R25
				CLR	R26
				CLR	R27
				CLR	R28
				CLR	R29
; End of initialization ==========================================

; Internal Hardware Init  ======================================
 
; End Internal Hardware Init ===================================
 
; External Hardware Init  ======================================
 
; End Internal Hardware Init ===================================
 
; Run ==========================================================
 
; End Run ======================================================

; Main =========================================================
	Main:
				NOP
				NOP
				NOP
				RJMP	Main
; End Main =====================================================

; Procedure ====================================================
 
; End Procedure ================================================

